Generally, in a data receiving device for a digital communication system, a synchronous clock for receiving data is recovered by using the extracted synchronous clock. To this end, a conventional clock recovery circuit generally uses a phase lock loop (hereinafter referred to as PLL).
Referring to FIG. 1, a conventional clock recovery circuit comprises a symbol transition detector 10 for detecting symbol transitions in the data stream input and supplying an input clock fi switching between logic "0" and logic "1" levels responsive to each symbol transition, a phase detector 12 for developing an error signal by comparing a phase of the input clock fi with a phase of an output clock fo fed back to the phase detector 12, a low pass filter 14 for eliminating a high-frequency component from that error signal and to supply a direct voltage component V.sub.d of that error signal, and a voltage-controlled oscillator (or VCO) 16 for adjusting the frequency of the output clock fo in accordance with V.sub.d. The phase detector 12, the low pass filter 14 and the VCO 16 form the PLL that locks the frequency of the output clock fo output from the VCO 16 in quadrature phasing with the input clock fi, so the nominal phase between the input clock fi and the output clock fo is 90.degree.. Accordingly, sampling of each input data bit can be executed on a rising edge of the output clock fo, so as to sample the bit at the time most likely to result in accurate data recovery.
The PLL in the FIG. 1 clock recovery circuit operates as an automatic frequency and phase control (AFPC) loop for controlling both the frequency and the phase of the VCO 16. Variants of the FIG. 1 clock recovery circuit are known to be possible in which the frequency and phase control functions are advantageously kept separate, with the PLL just controlling the phase of the clock signal supplied to the data sampler and to the phase detector 12. In such a variant, the frequency of the VCO 16 is controlled independently of phase using control signal supplied by a very long-time constant automatic frequency control (AFC) loop, rather than using V.sub.d as its control signal; and the VCO is followed by a phase controller that responds to the VCO output signal to supply clock signal to the data sampler and to the phase detector 12 in a phase determined by the V.sub.d response of the PLL lowpass filter 14.
Conventional clock recovery circuits based upon the PLL structure, as exemplified by the FIG. 1 clock recovery circuit or the described variant thereof, function satisfactorily in maintaining quadrature phasing between the input clock fi and the output clock fo when the clock is recovered from a data bit stream received at a relatively low speed. But such a clock recovery circuit does not maintain such quadrature phasing satisfactorily when the clock has to be recovered from input data having high data bit transmission speeds (e.g., of a gigahertz or more), so the accuracy of data recovery is compromised.
As the data rate goes up and the frequency of the input clock fi and the output clock fo is correspondingly increased, the period of these clocks being inversely related to their frequency is reduced, so small amounts of time delay represent a larger amounts of phase shift in terms of radians or degrees. The PLL is a feedback loop that can be analyzed as a tracking filter, by referring the performances of its constituent parts to baseband. The stability of a feedback loop is determined by phase margin, the number of radians or degrees of additional open-loop phase shift as referred to baseband that are required to make the feedback loop regenerative, rather than degenerative, in operation. As the frequency of the output clock fo is increased to accommodate higher data bit transmission speeds, the incidental delay the fedback output clock fo encounters in the phase detector 12 decreases the open-loop phase margin by proportionately larger amounts, which eventually leads to the loss of tracking capability.
Other clock recovery schemes which rely on phase lock loops are known in the prior art, which use different phase detectors to determine when data is not optimally sampled. The problem of the loss of tracking capability as baud rate goes up and symbol periods shorten is also noted in these other types of PLL.